Clustered surface preparation for silicide and metal contacts

ABSTRACT

A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a cluster tool for the implementing ofa clustered and integrated surface pre-cleaning of the surface ofsemiconductor devices. More particularly, the invention is directed tothe provision of a cluster tool and to a method of utilization thereofin an integrated semiconductor device surface pre-cleaning, which isdirected towards a manufacturing aspect in which a chamber forperforming a dry processing chemical oxide removal (COR) on thesemiconductor device surface is clustered with other tools, such as ametal deposition tool for silicide or contact formation, including theprovision of a vacuum transfer module in the cluster tool.

Extensive experimentation and physical applications have beenimplemented in connection with the preparation of surfaces ofsemiconductor devices for the formation of silicide and metal contacts,employing so called cluster tools wherein, in particular, in order toeffectuate the removal of surface films and thin layers of oxides, thereare provided advantages in contrast with conventional wet etch basedprocess flows.

Pursuant to the current state-of-the-art, which is concerned withvarious technical and economic aspects of semiconductor processing andmanufacture, in order to fulfill a need for small or miniaturizedgeometries and improved performance characteristics, the contact modulehas attained an increased significance as an important element of chipyield and semiconductor device performance. For instance, in thecurrently employed 65 nm and 45 nm technologies, the requirements for ahigh-strength and low-resistance electrical path which make contact tothe semiconductor device, are criteria which define limitations in theperformance of the device.

Thus, in order to address the problems which are encountered by suchperformance limitations, consideration can be applied to techniquesinvolving the applicability of chemical oxide removal (COR) basedprocesses to the removal of deleterious surface oxides on thesemiconductor surfaces which may present an impediment to the enablingof a good ohmic contact to semiconductor devices. In this connection,the presence of oxygen interfaces and oxygen contamination are seriousproblems encountered in contact module formulations and may result insignificant performance and yield losses in advanced technology nodes.

To a significant extent, this problem has been addressed in U.S. Pat.Nos. 5,184,132 B1 and 5,282,925; and U.S. Patent Publication No.2001/0001298 A1, all of which are commonly assigned to the assignee ofthis application, and the contents of which are incorporated herein intheir entireties; and wherein U.S. Pat. No. 5,282,925 is discussed infurther detail in connection with the present invention.

2. Discussion of the Prior Art

Pyo, et al., U.S. Patent Publication No. 2004/0092101 A1, discloses aCu-thin film deposition equipment for a semiconductor device, which isintended to improve the speed of depositing a Cu-thin film, andresultingly lowering the corresponding manufacturing costs. Althoughthere is provided a load lock for carrying out the film deposition stepsbefore and after wafer processes, and wherein an aligner effectuatesalignments so that a wafer reaches a desired position, a degassingchamber removes residue, such as gas produced on the surface of a wafer,whereas a feeding chamber is provided with a robot placing the waferinto and out of each chamber. There is no disclosure or suggestion ofproviding for a dry processing method comprising a chemical oxideremoval (COR) of a surface film in a cluster tool, as in the presentinvention so as to provide for surface preparation for silicide andmetal contacts on semiconductor devices.

Bae, et al., U.S. Patent Publication No. 2002/0162742 A1, describes acluster tool for forming semiconductor devices using a wafer processincluding at least one load port at which wafers are loaded and whereina front end system uses an ATM (atmosphere) robot and ATM aligner. Thereis no disclosure of employing a vacuum transfer system and cluster toolfor chemical oxide removal, nor a dry processing operation to prepare asurface of a semiconductor device for silicide or metal contacts, as inthe present invention.

Yoo, U.S. Patent Publication No. 2002/0144904, discloses a processingsystem and related method for vacuum evaporation of a material layer orfilm on a substrate. However, although there is provision made for aseries of pumps for selecting processing pressure levels without theneed for lowering the pressure to deep vacuum pressure conditions, thereis no disclosure of a dry processing chamber to provide for chemicaloxide removal (COR), which is clustered with other tools, so as toprepare a clustered surface for silicide or metal contact formation on asemiconductor device.

Kobayashi, et al., U.S. Pat. No. 6,776,874 B2 discloses a processingmethod and apparatus for removing oxide films from a surface of anobject which is to be treated through the intermediary of various gastreatments. However, there is no disclosure of a cluster tool and methodutilizing a dry processing chamber for chemical oxide removal, includinga metal deposition tool with a vacuum transfer module pursuant to thepresent invention, adapted to prepare a surface for silicide or metalcontact formation.

Similarly, Lee, et al., U.S. Pat. No. 6,586,340 B2 and Gilboa, et al.,U.S. Pat. No. 6,204,120 B1 disclose various pre-treatment methods forsemiconductor wafers, and for subsequent processing, including transferchambers and pluralities of vacuum conditions for removing native oxidefilms from the surface of a subject, such as cluster type wafers or thelike. However, there is no description of a clustered surfacepreparation for silicide and metal films to form contacts in a dryprocess pre-cleaning (COR) operation using a clustered tool providingchemical oxide removal chambers and metal deposition chambers inconjunction with vacuum transfer chambers and load lock clusterarrangements, as is described by the present invention.

SUMMARY OF THE INVENTION

The present invention, in order to provide an advance in the processingof semiconductor devices, is, accordingly, directed to the provision ofan integrated work tool and method for the clustered surface preparationof a semiconductor surface for the formation of silicide and metalcontacts possessing low-resistance and high-ohmic electrical pathcharacteristics. The inventive concept entails the utilization of thechemical oxide removal (COR) process of eliminating surface oxide films,such as native oxide, as an integrated process with coordinatedsubsequent metal depositions for silicide or contact formation.

Accordingly, in order to clearly distinguish and improve over the priorart, pursuant to the present invention, there is provided a cluster toolarrangement for a pre-cleaning oxide film removing surface preparationfor enabling silicide and metal depositions on semiconductor devices byemploying a cleaner integrated processing without a vacuum break andthrough an improved interface control. In particular, pursuant to theinvention, the cluster tool arrangement replaces the current wet-etchbased process flow by the provision of a dry method of processing whichreduces the usage of wet chemicals and enables a cleaner application forsurface preparation prior to implementing any metal deposition.

In particular, the invention utilizes a chemical oxide removal (COR)process and chamber, for instance, such as in U.S. Pat. No. 5,282,925;which selectively is employed among various types of oxides, such asnative oxide, possibly employing gaseous nitrogen trifluoride (NF₃), orother gaseous mediums, which can conserve STI and control recess of theisolation so as to form improved silicides, for example, such as cobaltsilicide, or suitable metals, such as titanium nitride, without anyexcessive STI oxide losses. Other patents and publications which aredirected to the implementation of the COR process are U.S. Pat. No.6,184,132 B1 and U.S. Patent Publication No. 2001/0001298 A1; which arecommonly assigned to the present assignee, and the disclosures of whichare incorporated herein in their entireties.

An even more specific advantage of the inventive dry processing usingCOR over wet processing is a differentiator for SOI technologies and, inparticular, where contact to Box leakage is a major concern. In thisconnection, the SOI structures include an insulating layer, in effect, aburied oxide region (BOX), which, for instance, electrically isolates atop Si-containing layer from a bottom Si-containing layer, and whereinthe top Si containing, or, in effect, the SOI layer serves as the areain which electronic devices, such as MOSFET (metal oxide semiconductorfield effect transistor) devices are imparted a high degree of yield andefficiency.

Another improvement over the art provided for by the present inventionrelates to reduced queue times for processing lines, and improved rawprocessing times for the manufacture of contact and silicide modules.

Accordingly, it is an object to provide an improved and novel clusteredsurface preparation tool for an oxide-removing pre-cleaning andpreparation for the silicide and metal contacts on semiconductordevices.

Another object resides in the provision of a method of providing for adry-process based chemical oxide removal method employed in thepre-treatment of clustered and integrated surfaces for silicide andmetal contact preparation for semiconductor devices and modules.

Yet another object resides in the provision of a cluster tool for thepreparation of silicide and metal surfaces without a vacuum break andbetter interface control employing a cluster tool comprising a CORpre-clean chamber, a metal deposition chamber including a vacuum chamberin connection with a load lock for the rapid dry processing ofsemiconductor surfaces.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference may now be made to the following detailed description of apreferred embodiment of the invention, taken in conjunction with theaccompanying drawings, in which:

FIG. 1 illustrates a cluster tool arrangement for the surfacepre-cleaning of a semiconductor device in a COR chamber, and which isintegrated with the preparation of silicide and metal contacts; and

FIG. 2 illustrates, generally diagrammatically, an apparatus forimplementing the chemical oxide removal (COR) process, as known in theprior art.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1 of the drawings, there is diagrammaticallyillustrated a cluster tool arrangement 10, comprising a vacuum transferchamber 12, and providing for a first load lock 14 and a second loadlock 16 for the transferring in and removal of workpieces, such assemiconductor wafers (not shown), which are to be pre-cleaned in a (COR)chamber 18 by means of a dry process consisting of chemical oxideremoval (COR) methods, and then treated in a metal deposition chamber20. The load-locks 14, 16; COR pre-cleaning chamber 18 and metaldeposition chamber 20 are clustered about the vacuum through chamber 12.

Referring, in particular, to the schematic representation, asillustrated in FIG. 2 of the drawings, this discloses, diagrammatically,the pre-treatment chemical oxide removal (COR) chamber 18, which isemployed in connection with the cluster tool arrangement 10, pursuant tothe present invention.

In particular, the pre-treatment COR chamber 18, as diagrammaticallydisclosed herein, is described in detail in particular connection withFIG. 4 of Jeng, et al., U.S. Pat. No. 5,282,925, which is commonlyassigned to the present assignee, and the disclosure of which isincorporated herein in its entirety.

In this connection, the CDR pre-treatment chamber 18 provides for alow-pressure and plasma-free and damage-free etching of silicon dioxideon a wafer surface, wherein the wafer is represented by referencenumeral 30 in the drawing.

Hereby, the pre-treatment chamber 18 is provided with water through thepassageway 32, wherein the wafer 30 is positioned on the upper surfaceof the support structure 34 and may be heated by means of a suitableheating arrangement, such as coils 36 or the like.

The pressure in the pre-treatment chamber 18 may be suitably controlled,as is described in the foregoing U.S. Pat. No. 5,282,925 and gaseousmixtures of ammonia (NH₃) and hydrogen fluoride HF are injected into theinterior of the chamber 18 through respective inlet conduits 38 and 40.

In effect, through suitably controlled pressure and temperatureconditions, as described in U.S. Pat. No. 5,282,925, chemical oxideremoval (COR) is implemented in an essentially two-step reaction inwhich in a first step, solid reaction product (NH₄)₂SiF₆ is formed onthe oxide surface which is present on the wafer 30 and self limits thereaction. This enables a controlled removal of oxide for the wafersurface pre-clean preparation. Thereafter, in a second step, thereaction product is removed through discharge sublets 42, 44 by heating(sublimination) responsive to the heat of the reaction being controlled(not shown) by a suitable controller acting on heating coils 36, thelatter of which are diagrammatically represented in the drawing.

The particular conditions for the implementation of the chemical oxideremoval (CDR) process are detailed in the disclosure of U.S. Pat. No.5,282,925 and a detailed repetition thereof in the present specificationis deemed to be unnecessary for an understanding of the invention.

In particular, the cluster tool arrangement 10 provides for a selectivecleaning of different types of oxides from the surfaces of thesemiconductor device or wafer so as to control and conserve STI oxidelosses. Hereby, the semiconductor device or wafer is transported into arespective load lock 14, 16, and from there into vacuum transfer chamber12. Thereafter, under vacuum condition, the wafer (or semiconductordevice) is conveyed into pre-cleaned chamber 18, which basicallycomprises the COR (chemical oxide removal) apparatus for effecting anoxide-removing cleaning sequence on the wafer surface Upon completion ofthe removal of oxide film or surface deposition, the wafer is thentransferred back to the vacuum transfer chamber 12 and then into metaldeposition chamber 20, where the appropriate metal deposition ofsuicides or other metals, as known, is imparted to the surface of thesemiconductor device or wafer to produce the desired contacts possessinghigh-strength and high-ohmic electrical path characteristics. The wafermetal or silicide-forming surface preparation having been completed, thewafer or semiconductor module is transferred back to the vacuum transferchamber 12 and from there to one of the load locks 14 or 16 for furtherconveyance and processing at a further site in accordance with theprevailing technology.

While the present invention has been particularly shown and describedwith respect to preferred embodiments, it will be understood by thoseskilled in the art that the foregoing and other changes in forms anddetails may be made without departing from the spirit and scope of thepresent invention. It is therefore intended that the present inventionnot be limited to the exact forms and details described and illustrated,but fall within the scope of the appended claims.

1-9. (canceled)
 10. A cluster tool arrangement for the integratedpre-cleaning of a semiconductor surface and surface preparation forforming metal and silicide contacts thereon; comprising: at least oneload lock for receiving a semiconductor having an oxide on one surfacethereof; a transfer chamber for receiving said semiconductor from saidat least one load lock under a vacuum condition; a pre-treatment chamberfor receiving said semiconductor from said transfer chamber, whilemaintaining said vacuum condition, said substrate being subjected to adry chemical oxide removal (COR) treatment in said pre-treatment chamberto remove the oxide from said semiconductor surface, and thereafter,re-convey said semiconductor to said transfer chamber; and a metaldeposition chamber for receiving said pre-cleaned substrate from saidtransfer chamber for depositing metal on said semiconductor surface andform a silicide on said surface to produce contacts.
 11. A cluster toolarrangement as claimed in claim 10, wherein a further said load lockreceives said substrate from said transfer chamber subsequent to theforming of said silicide on said semiconductor surface and upon saidsemiconductor being transferred from said metal deposition chamber tosaid transfer chamber.
 12. A cluster tool arrangement as claimed inclaim 10, wherein said arrangement is maintained under a continuousvacuum condition.
 13. A cluster tool arrangement as claimed in claim 10,wherein said pre-cleaning chamber contains a gaseous medium for removingsaid oxide from the surface of said semiconductor.
 14. A cluster toolarrangement as claimed in claim 13, wherein said gaseous mediumcomprises nitrogen trifluoride (NF₃).
 15. A cluster tool arrangement asclaimed in claim 10, wherein said metal is cobalt.
 16. A cluster toolarrangement as claimed in claim 15, wherein said silicide is cobaltsilicide.
 17. A cluster tool arrangement as claimed in claim 10, whereinsaid metal is titanium.
 18. A cluster tool arrangement as claimed inclaim 17, wherein metal is formed into metal nitride, which is depositedon said semiconductor surface in said metal deposition chamber toproduce contacts.
 19. A cluster tool arrangement as claimed in claim 10,wherein said transfer chamber, pre-treatment chamber and metaldeposition chamber are maintained under continuous vacuum conditions.